DRAM

Dynamic Random Access Memory (DRAM) stores each bit of data in a separate capacitor within and integrated circuit; unless the capacitor charge is refreshed regularly the data will eventually fade. It is because of the this refresh requirement that it is know as dynamic memory as opposed to the flash used in SSD which is static memory. 

The advantage of DRAM is its simplicity, only one transistor and one capacitor is required per bit, this allows it to reach very high density. Today’s server and storage manufacturers use DRAM in for quick access to regularly used data which can be cached in the DRAM as opposed to being held on the slower media within the systems disk drives.

DRAM specifications

DRAM comes in various specifications and formats as follows:

• SIMM - Single Inline Memory Module. The gold pins on the lower edge of the front and back of a SIMM are connected, providing a single line of communication paths between the module and the system. 
• DIMM - Dual Inline Memory Module. The pins on a DIMM are not connected, providing two lines of communication paths between the module and the system, one in the front and one in the back. 
• SO-DIMM - Small Outline Dual Inline Memory Module. For use in embedded and mobile devices such as notebooks.

Registered DRAM (also informally called buffered) memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise. (unbuffered = not registered)

Memory modules with ECC (error correction code) include extra memory bits that allows a single-bit error to be corrected and (in the usual configuration, with an extra parity bit) double-bit errors to be detected. ECC modules are configured by x72 (compared to non-ECC x64) e.g.  2GB module is 256Mx72 (ECC) and 256Mx64 (non-ECC) 

Chipkill is IBM's trademark for a form of advanced Error Checking and Correcting (ECC) computer memory technology.

CAS latency (CL) is the delay time which elapses between the moment a memory controller tells the memory module to access a particular column in a selected row, and the moment the data from the given array location is available on the module's output pins.

Fully Buffered DIMM (or FB-DIMM) is a memory technology which can be used to increase reliability, speed and density of memory systems.  It introduces an Advanced Memory Buffer (AMB) between the memory controller and the memory module. Unlike the parallel bus architecture of traditional DRAM’s, an FB-DIMM has a serial interface between the memory controller and the AMB. With this architecture, the memory controller does not write to the memory module directly, rather it is done via the AMB. The AMB can also offer error correction.

A DIMM's capacity and timing parameters are be identified with SPD (Serial Presence Detect), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. 

A Rank is a distinct, independent addressable 64bit-width (72bit for ECC) area of a memory module. Each rank behaves as a separate module. DIMM’s are available with 1, 2 or 4 ranks (Single, Dual and Quad-Rank-DIMM’s). Chipsets can manage usually only up to 8 ranks.